1. Technical Field
The present invention generally relates to synchronized electronic systems, and more particularly to a method of dynamically adjusting the duty cycle of a clock signal in a digital computer system having a clock distribution network.
2. Description of Related Art
Many modern electronic systems require a precise clock circuit for proper operation. For example, digital information processing equipment such as a computer must have an accurate and reliable clock source to control the various signals that are sent between the functional components of the computer. In such systems, it is very important that all of the components are properly synchronized to a common clock.
Synchronous electronic equipment utilizes an oscillator circuit to produce a basic source frequency signal. This signal is in turn utilized to drive other circuitry (such as a phase-lock loop, or PLL) for developing desired rise and fall times of square-wave signals, and desired signal levels. The clock rate requirements for timing digital information processing systems are generally proportional to the switching speeds of the circuitry employed. As clock circuits improve and clock rates increase, tolerances are necessarily diminished, and clock skew becomes an ever-increasing problem.
Different problems can arise in the accuracy of the clock signal. Variations in timing between successive 5 rising edges (or falling edges), i.e., the overall cycle variation (often referred to as xe2x80x9cjitterxe2x80x9d) typically relates to the oscillator. Variations in the duty cycle (the portion of the overall cycle in which the signal is xe2x80x9conxe2x80x9d), i.e., between a rising edge and the next falling edge, typically relate to the clock distribution network, although variations in the duty cycle can also be caused by the oscillator. Clock distribution networks use various elements such as buffers and inverters, often cascaded. These networks can introduce duty cycle distortion due to circuit and interconnect modeling inaccuracies, process variations, and the environment.
For systems which use both the rising and falling edges for timing, a non-optimal clock duty cycle may require a lower clock frequency, reducing performance. A duty cycle error of just 5% for instance (from 50% to 45%) may require a system clock to run at a maximum speed that is 10% lower, causing a significant impact on system performance. Many circuits require a specific duty cycle for clocking signals to provide optimal performance. For example, multi-phase clocking systems often require a symmetrical wave shape that is characteristically desired to operate at a 50% duty cycle. Some applications require a duty cycle other than 50%. One use of non-50% duty cycles is in digital clocking where pulse-mode latching is used rather than edge-latching in order to reduce the setup-hold overhead associated with the latches.
Actual duty cycles typically do not have precisely the desired value. Even if a clock signal has the required duty cycle at some point in the system (e.g., at the output of an on-chip voltage-controlled oscillator), the duty cycle will deviate from the required percentage as the clock signal is buffered and distributed throughout the chip. Different approaches have been devised to actively control the duty cycle. Most of these approaches involve measurement of the error in the duty cycle, and provision of a correction signal to reduce that error.
For example, Gronowski et al., in xe2x80x9cA 433 MHz 64b Quad-Issue RISC Microprocessor,xe2x80x9d ISSCC Digest, pp. 222-223 (February 1996), describe a technique in which the duty cycle is monitored and a feedback mechanism changes the delay in an off-chip clock receiver circuit. In the article by Nakamura et al., xe2x80x9cA CMOS 50% Duty Cycle Repeater Using Complementary Phase Blending,xe2x80x9d VLSI Circuits Digest, pp. 48-49 (June 2000), a system is disclosed requiring two clock phases for a unique xe2x80x9cphase-blendingxe2x80x9d mechanism. Another system, disclosed in Jung et al., xe2x80x9cA Low-Jitter Dual Loop DLL Using Multiple VCDLs With a Duty Cycle Corrector,xe2x80x9d VLSI Circuits Digest, pp. 50-51 (June 2000), also requires two clock phases. That design, however, utilizes a feedback control architecture as well. In U.S. Pat. No. 5,491,440, a circuit compares the average output value of a monostable multivibrator with a reference voltage, and increments or decrements a counter which drives a data port on the monostable multivibrator. U.S. Pat. No. 6,084,452 describes a clock duty cycle control technique which compares a reference voltage generated by Vdd and ground, and a comparison signal using feedback. The adjustment circuit uses differential amplifiers to shift a reference voltage for adjustment of the duty cycle of the VCO signal.
All of the foregoing techniques add a new level of complexity to the clock distribution scheme. All of these techniques also apply to bulk semiconductor technology, and may be unsuitable for other fabrication methodologies, such as a silicon-on-insulator (SOI) process. It would, therefore, be desirable to devise an improved clock distribution network having a more consistent and accurate duty cycle. It would be further advantageous if the duty cycle adjustment could be accomplished without significantly adding to the complexity of the distribution network.
It is therefore one object of the present invention to provide improved clocking control for a synchronized electronic system.
It is another object of the present invention to provide an improved clock distribution network which reduces duty cycle variations.
It is yet another object of the present invention to provide such an improved clock distribution network which dynamically adjusts the duty cycle without adding significant expense.
The foregoing objects are achieved in a method of controlling a clock signal for an electronic system, generally comprising the steps of detecting an error in a duty cycle of a clock signal in a clock distribution network of the electronic system, and dynamically adjusting a body voltage of at least one electronic device in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. For example, if the clock distribution network includes an inverter chain having a plurality of inverters, wherein each of the inverters has at least one p-type device and one n-type device, the adjustment may be performed by adjusting the body voltages of the p-type devices in odd-numbered ones of the inverters while adjusting the body voltages of the n-type device in even-numbered ones of the inverters to affect a falling edge of the clock signal, and adjusting the body voltages of the p-type devices in even-numbered ones of the inverters while adjusting the body voltages of the n-type device in odd-numbered ones of the inverters to affect a rising edge of the clock signal.
In one implementation, the body voltage of the electronic device is adjusted by selectively connecting a body contact of the device to one of a plurality of discrete voltages using a multiplexer. If the electronic device is a p-type device, the body contact may be connected to one of a plurality of power supplies and, if the electronic device is an n-type device, the body contact may be connected to one of a plurality of reference planes. Alternatively, the invention may be implemented in an analog fashion, such as by applying an analog signal to the body contact, wherein the analog signal is generated using an asymmetric charge-pump and filter connected to the clock signal.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.